

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity Test_Disp is
Port (clk: in bit;
		--mode : in integer range 0 to 3;
	  led_dig0: in integer range 0 to 15;
	  led_dig1: in integer range 0 to 15;
	  led_dig2: in integer range 0 to 15;
	  led_dig3: in integer range 0 to 15;
  	  led_dig_out : out std_logic_vector(7 downto 0);
  	  led_en_out : out std_logic_vector(3 downto 0));
end Test_Disp;

architecture Behavioral of Test_Disp is

signal slow: integer range 0 to 511;
type int_table is array (0 to 15) of std_logic_vector(7 downto 0);
signal cur_dig: integer range 0 to 3 := 0;
constant IT : int_table := (	"11000000", 
	            			           "11111001", 
	     					           "10100100",
	     					           "10110000", 
	      				              "10011001", 
            			              "10010010",
	      				              "10000010", 
            			              "11111000",
            			              "10000000", 
							        "10010000",
                           		"10001000",
                           		"10000011",
                           		"11000110",
                           		"10100001",
                           		"10000110",
                          		"10001110"); 

begin

process (clk)
begin
if (clk'event and clk = '0') then
  if slow = 511 then
	  if cur_dig = 0 then
		  led_dig_out <= IT(led_dig0);
		  led_en_out <= "1110";
		  cur_dig <= 1;
	  elsif cur_dig = 1 then
		  led_dig_out <= IT(led_dig1);
		  led_en_out <= "1101";
		  cur_dig <= 2;
	  elsif cur_dig = 2 then
		  led_dig_out <= IT(led_dig2);
		  led_en_out <= "1011";
		  cur_dig <= 3;
	  else
		  led_dig_out <= IT(led_dig3);
		  led_en_out <= "0111";
		  cur_dig <= 0;	
	  end if;
	  slow <= 0;
  else
	  slow <= slow + 1;
  end if;  
else
  null;
end if;
end process;
end Behavioral;

